Digital - RTL Design Quality & Automation Engineer

Lint / CDC / Synthesis Quality -- AI-Augmented Design Flows - CI/CD for RTL On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON  Full-Time - Equity Participation - Comprehensive Benefits   ABOUT THE ROLE Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.  Here is the honest version of this job. Our digital designers spend part of every week doing work a machine should be doing: re-running lint and CDC by hand, reading thousands of violations to find the twenty that matter, chasing down which synthesis run regressed QoR, and manually assembling the evidence that a branch is clean enough to promote to release.    We are looking for an engineer who can own the intersection of design quality and design automation. In this role you will define and enforce signoff criteria for lint, CDC, and synthesis across all active programs, build the waiver management and tracking infrastructure, and develop AI-augmented tooling that turns thousands of tool violations into actionable, designer-ready reviews. You will report into the digital design team and work directly alongside RTL designers — this is not a pure DevOps or IT role.